Allwinner A20 - Page 142

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 142 / 812
1) HS timer 1 current value is a 56-bit down-counter (from interval value to 0).
2) The current value register is a 56-bit register. When read or write the current value, the Low
register should be read or written first.
1.10.3.13. HS TIMER 2 CONTROL REGISTER (DEFAULT: 0X00000000)
Offset:0x50
Register Name: HS_TMR2_CTRL_REG
Bit
Read/
Write
Default/He
x
Description
31
R/W
0x0
/
30:8
/
/
/
7
R/W
0x0
HS_TMR2_MODE.
High Speed Timer 2 mode.
0: Continuous mode. When interval value reached, the timer will
not disable automatically.
1: Single mode. When interval value reached, the timer will
disable automatically.
6:4
R/W
0x0
HS_TMR0_CLK
Select the pre-scale of the high speed timer 0 clock sources.
000: /1
001: /2
010: /4
011: /8
100: /16
101: /
110: /
111: /
3:2
/
/
/
1
R/W
0x0
HS_TMR2_RELOAD.
High Speed Timer 2 Reload.
0: No effect, 1: Reload High Speed Timer 2 Interval Value.
0
R/W
0x0
HS_TMR2_EN.
High Speed Timer 2 Enable.
0: Stop/Pause, 1: Start.
If the timer is started, it will reload the interval value to internal
register, and the current counter will count from interval value to
0.
If the current counter does not reach the zero, the timer enable
bit is set to “0”, the current value counter will pause. At least wait