Allwinner A20 - Page 165

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 165 / 812
1.12.3.6. NORMAL DMA DESTINATION ADDRESS REGISTER(DEFAULT:
0X00000000)
Offset: 0x100+N*0x20+0x8
(N=0,1,2,3,4,5,6,7)
Register Name: NDMA_DEST_ADDR_REG
Bit
Read/
Write
Default/Hex
Description
31:0
R/W
0x0
NDMA_DEST_ADDR.
Normal DMA Destination Address.
1.12.3.7. NORMAL DMA BYTE COUNTER REGISTER(DEFAULT: 0X00000000)
Offset: 0x100+N*0x20+0xC
(N=0,1,2,3,4,5,6,7)
Register Name: NDMA_BC_REG
Bit
Read/
Write
Default/Hex
Description
31:18
/
/
/.
17:0
R/W
0x0
NDMA_BC.
Normal DMA Byte Counter.
Note: If ByteCounter=0, DMA will transfer no byte. The maximum value is 128k.
1.12.3.8. DEDICATED DMA CONFIGURATION REGISTER(DEFAULT: 0X00000000)
Offset:
0x300+N*0x20
(N=0,1,2,3,4,5,6,7)
Register Name: DDMA_CFG_REG
Bit
Read
/Write
Default/Hex
Description
31
R/W
0x0
DMA_LOADING.
DMA Loading.
If set to 1, DMA will start and load the DMA registers to the
shadow registers. The bit will hold on until the DMA finished. It
will be cleared automatically.
Set 0 to the bit will stop the corresponding DMA channel and
reset its state machine.
30
R
0x0
DMA_BSY_STA.
DMA Busy Status.