Allwinner A20 - Page 166

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 166 / 812
Offset:
0x300+N*0x20
(N=0,1,2,3,4,5,6,7)
Register Name: DDMA_CFG_REG
Bit
Read
/Write
Default/Hex
Description
0: DMA idle, 1: DMA busy.
29
R/W
0x0
DMA_CONT_MODE_EN.
DMA Continuous Mode Enable.
0: Disable, 1: Enable.
28
R/W
0x0
DMA_DEST_SEC.
DMA Destination Security.
0: secure, 1: non-secure
27
/
/
/.
26:25
R/W
0x0
DMA_DEST_DATA_WIDTH.
DMA Destination Data Width.
00: 8-bit
01: /
10: 32-bit
11: /
24:23
R/W
0x0
DMA_DEST_BST_LEN.
DMA Destination Burst Length.
00: 1
01: /
10: 8
11: /.
22:21
R/W
0x0
DMA_ADDR_MODE.
DMA Destination Address Mode
DMA Source Address Mode
0x0: Linear Mode
0x1: IO Mode
0x2: Horizontal Page Mode
0x3: Vertical Page Mode
20:16
R/W
0x0
DDMA_DEST_DRQ_TYPE.
Dedicated DMA Destination DRQ Type
0x0: SRAM memory
0x1: SDRAM memory
0x2:
0x3: NAND Flash Controller (NFC)
0x4: USB0
0x5: /