Allwinner A20 - Page 168

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 168 / 812
Offset:
0x300+N*0x20
(N=0,1,2,3,4,5,6,7)
Register Name: DDMA_CFG_REG
Bit
Read
/Write
Default/Hex
Description
10:9
R/W
0x0
DMA_SRC_DATA_WIDTH.
DMA Source Data Width.
00: 8-bit
01: /
10: 32-bit
11: /
8:7
R/W
0x0
DMA_SRC_BST_LEN.
DMA Source Burst Length.
00: 1
01: /
10: 8
11: /..
6:5
R/W
0x0
DMA_SRC_ADDR_MODE.
DMA Source Address Mode
0x0: Linear Mode
0x1: IO Mode
0x2: Horizontal Page Mode
0x3: Vertical Page Mode
4:0
R/W
0x0
DDMA_SRC_DRQ_TYPE.
Dedicated DMA Source DRQ Type
0x0: SRAM memory
0x1: SDRAM memory
0x2:
0x3: NAND Flash Controller (NFC)
0x4: USB0
0x5: /
0x6: /
0x7: Ethernet MAC Rx
0x8: /
0x9: SPI1 RX
0xA: /
0xB: Security System Rx
0xC: /
0xD: /
0xE: /
0xF: /