Allwinner A20 - Page 169

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 169 / 812
Offset:
0x300+N*0x20
(N=0,1,2,3,4,5,6,7)
Register Name: DDMA_CFG_REG
Bit
Read
/Write
Default/Hex
Description
0x10: /
0x11: /
0x12: /
0x13: /
0x14: /
0x15: /
0x16: /
0x17: Memory Stick Controller (MSC)
0x18: /
0x19: /
0x1A: /
0x1B: SPI0 RX.
0x1C: /
0x1D: SPI2 RX
0x1E: /
0x1F: SPI3 RX
1.12.3.9. DEDICATED DMA SOURCE START ADDRESS REGISTER
Offset: 0x300+N*0x20+0x4
(N=0,1,2,3,4,5,6,7)
Register Name: DDMA_SRC_START_ADDR_REG
Bit
Read/
Write
Default/He
x
Description
31:0
R/W
x
DDMA_SRC_START_ADDR.
Dedicated DMA Source Start Address.
1.12.3.10. DEDICATED DMA DESTINATION START ADDRESS REGISTER
Offset: 0x300+N*0x20+0x8
(N=0,1,2,3,4,5,6,7)
Register Name: DDMA_DEST_START_ADDR_REG
Bit
Read/
Write
Default/H
ex
Description
31:0
R/W
x
DDMA_DEST_START_ADDR.
Dedicated DMA Destination Start Address.