Allwinner A20 - Page 182

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 182 / 812
Offset: 0x1C
Register Name: AC_ADC_FIFOC
Bit
Read/Write
Default
Description
3
R/W
0x0
ADC_IRQ_EN.
ADC FIFO Data Available IRQ Enable.
0: Disable
1: Enable
2
/
/
/
1
R/W
0x0
ADC_OVERRUN_IRQ_EN.
ADC FIFO Over Run IRQ Enable
0: Disable
1: Enable
0
R/W
0x0
ADC_FIFO_FLUSH.
ADC FIFO Flush.
Write ‘1’ to flush TX FIFO, self clear to ‘0’.
1.13.4.8. ADC FIFO STATUS REGISTER
Offset: 0x20
Register Name: AC_ADC_FIFOS
Bit
Read/Write
Default
Description
31:24
/
/
/
23
R
0x0
RXA.
RX FIFO Available
0: No available data in RX FIFO
1: More than one sample in RX FIFO (>= 1 word)
22:14
/
/
/
13:8
R
0x0
RXA_CNT.
RX FIFO Available Sample Word Counter
7:4
/
/
/
3
R/W
0x0
RXA_INT.
RX FIFO Data Available Pending Interrupt
0: No Pending IRQ
1: Data Available Pending IRQ
Write ‘1’ to clear this interrupt or automatic clear if interrupt
condition fails.
2
/
/
/
1
R/W
0x0
RXO_INT.