Allwinner A20 - Page 183

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 183 / 812
Offset: 0x20
Register Name: AC_ADC_FIFOS
Bit
Read/Write
Default
Description
RX FIFO Overrun Pending Interrupt
0: No Pending IRQ
1: FIFO Overrun Pending IRQ
Write ‘1’ to clear this interrupt
0
/
/
/
1.13.4.9. ADC RX DATA REGISTER
Offset: 0x24
Register Name: AC_ADC_RXDATA
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:0
R
0x0
RX_DATA.
RX Sample
Host can get one sample by reading this register. The left
channel sample data is first and then the right channel sample.
1.13.4.10. ADC ANALOG CONTROL REGISTER
Offset:0x28
Register Name: AC_PA_ADC_ACTRL
Bit
R/W
Default
Description
31
R/W
0x0
ADCREN.
ADC Right Channel Enable
0-Disable
1-Enable
30
R/W
0x0
ADCLEN.
ADC Left Channel Enable
0-Disable
1-Enable
29
R/W
0x0
PREG1EN.
MIC1 pre-amplifier Enable
0-Disable
1-Enable
28
R/W
0x0
PREG2EN.
MIC2 pre-amplifier Enable