Allwinner A20 - Page 284

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 284 / 812
Offset: 0x104
Register Name: PH_CFG2
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
000: Input 001: Output
010: LCD1_D18 011: ERXCK
100: KP_OUT0 101: SMC_SCK
110: EINT18 111: CSI1_D18
7
/
/
/
6:4
R/W
0
PH17_SELECT
000: Input 001: Output
010: LCD1_D17 011: ETXD0
100: KP_IN7 101: SMC_VCCEN
110: EINT17 111: CSI1_D17
3
/
/
/
2:0
R/W
0
PH16_SELECT
000: Input 001: Output
010: LCD1_D16 011: ETXD1
100: KP_IN6 101: Reserved
110: EINT16 111: CSI1_D16
1.19.4.67. PH CONFIGURE REGISTER 3
Offset: 0x108
Register Name: PH_CFG3
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:15
/
/
/
14:12
R/W
0
PH27_SELECT
000: Input 001: Output
010: LCD1_ VSYNC 011: ETXERR
100: KP_OUT7 101: SDC1_D3
110: Reserved 111: CSI1_VSYNC
11
/
/
Reserved
10:8
R/W
0
PH26Select
000: Input 001: Output
010: LCD1_HSYNC 011: ECOL