Allwinner A20 - Page 30

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 30 / 812
Offset: 0x208
Register Name: IDLE_CNT0_CTRL_REG
Bit
Read/
Write
Default/Hex
Description
Idle Counter Clear Enable.
0: no effect, 1: to clear the idle Counter Low/Hi registers and it
will change to zero after the registers are cleared.
1.4.3.13. IDLE COUNTER 1 LOW REGISTER (DEFAULT: 0X00000000)
Offset: 0x210
Register Name: IDLE_CNT1_LOW_REG.
Bit
Read/
Write
Default/Hex
Description
31:0
R/W
0x0
IDLE_CNT1_LO.
Idle Counter 1 [31:0].
This counter clock source is 24MHz. If the CPU is in idle state,
the counter will count up in the clock of 24MHz.
Any write to this register will clear this register and the idle
counter 1 high register.
1.4.3.14. IDLE COUNTER 1 HIGH REGISTER (DEFAULT: 0X00000000)
Offset: 0x214
Register Name: IDLE_CNT1_HIGH_REG
Bit
Read/
Write
Default/Hex
Description
31:0
R/W
0x0
IDLE_CNT1_HI.
Idle Counter 1[63:32].
Any write to this register will clear this register and the idle
counter 1 low register.
1.4.3.15. IDLE COUNTER 1 CONTROL REGISTER (DEFAULT: 0X00000000)
Offset: 0x218
Register Name: IDLE_CNT1_CTRL_REG
Bit
Read/
Write
Default/Hex
Description
31:3
/
/
/
2
R/W
0x0
IDLE_CNT_EN.
Idle counter enable.