Allwinner A20 - Page 335

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 335 / 812
3.1.4.27. OUTPUT CONTROL REGISTER
Offset: 0xE0
Register Name: MP_OUTCTL_REG
Bit
Read/W
rite
Default/
Hex
Description
31:12
/
/
/
11:8
R/W
0
OUT_PS
Output data pixel sequence
Reference output pixel sequence table
7
R/W
0
RND_EN
Round enable
0:disabled
1:enabled
6:4
/
/
/
3:0
R/W
0
OUT_FMT
Output data format
0x0: 32bpp – A8R8G8B8 or interleaved AYUV8888
0x1: 16bpp – A4R4G4B4
0x2: 16bpp – A1R5G5B5
0x3: 16bpp – R5G6B5
0x4: 16bpp – interleaved YUV422
0x5: planar YUV422 (UV combined)
0x6: planar YUV422
0x7: 8bpp – MONO
0x8: 4bpp – MONO
0x9: 2bpp – MONO
0xa: 1bpp – MONO
0xb: planar YUV420 (UV combined)
0xc: planar YUV420
0xd: planar YUV411 (UV combined)
0xe: planar YUV411
Other: reserved
Note: In all YUV output data format, the CSC2 must be enabled,
otherwise the output data mode will be 32bpp A8R8G8B8 mode.