Allwinner A20 - Page 413

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 413 / 812
5.1.4.5. TCON0 DATA CLOCK REGISTER
Offset: 0x044
Register Name: TCON0_DCLK REG
Bit
Read/
Write
Default/
Hex
Description
31:28
R/W
0
TCON0_Dclk_En
LCLK_EN[3:0] :TCON0 clock enable
4’h0,
‘h4,4’h6,4’ha7:dclk_en=0;dclk1_en=0;dclk2_en=0;dclkm2_en=0;
4’h1: dclk_en = 1; dclk1_en = 0; dclk2_en = 0; dclkm2_en = 0;
4’h2: dclk_en = 1; dclk1_en = 0; dclk2_en = 0; dclkm2_en = 1;
4’h3: dclk_en = 1; dclk1_en = 1; dclk2_en = 0; dclkm2_en = 0;
4’h5: dclk_en = 1; dclk1_en = 0; dclk2_en = 1; dclkm2_en = 0;
4’h8,4’h9,4’ha,4’hb,4’hc,4’hd,4’he,4’hf:
dclk_en = 1;
dclk1_en = 1;
dclk2_en = 1;
dclkm2_en = 1;
27:7
/
/
/
6:0
R/W
0
TCON0_Dclk_Div
Tdclk = Tsclk * DCLKDIV
Note:
1.if dclk1&dclk2 used,DCLKDIV >=6
2.if dclk only,DCLKDIV >=4
5.1.4.6. TCON0 BASIC TIMING REGISTER0
Offset: 0x048
Register Name: TCON0_BASIC0_REG
Bit
Read/
Write
Default/
Hex
Description
31:27
/
/
/
26:16
R/W
0
TCON0_X
Panel width is X+1
15:11
/
/
/