Allwinner A20 - Page 414

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 414 / 812
Offset: 0x048
Register Name: TCON0_BASIC0_REG
Bit
Read/
Write
Default/
Hex
Description
10:0
R/W
0
TCON0_Y
Panel height is Y+1
5.1.4.7. TCON0 BASIC TIMING REGISTER1
Offset: 0x04C
Register Name: TCON0_BASIC1_REG
Bit
Read/
Write
Default/
Hex
Description
31
R/W
0
UF_En
0: default
1: delay next line sync(Hsync in basic timing) until the FIFO1 is full
Note: it must be used when FIFO depth is less than one line active
pixels.
30:28
/
/
/
27:16
R/W
0
HT
Thcycle = (HT+1) * Tdclk
Note:1) parallel :HT >= (HBP +1) + (X+1) +2
2) serial 1: HT >= (HBP +1) + (X+1) *3+2
3) serial 2: HT >= (HBP +1) + (X+1) *3/2+2
15:10
/
/
/
9:0
R/W
0
HBP
horizontal back porch (in dclk)
Thbp = (HBP +1) * Tdclk
5.1.4.8. TCON0 BASIC TIMING REGISTER2
Offset: 0x050
Register Name: TCON0_BASIC2_REG
Bit
Read/
Write
Default/
Hex
Description
31:28
/
/
/
27:16
R/W
0
VT
TVT = (VT)/2 * Thsync
Note: VT/2 >= (VBP+1 ) + (Y+1) +2