Allwinner A20 - Page 415

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 415 / 812
Offset: 0x050
Register Name: TCON0_BASIC2_REG
Bit
Read/
Write
Default/
Hex
Description
15:10
/
/
/
9:0
R/W
0
VBP
Tvbp = (VBP +1) * Thsync
5.1.4.9. TCON0 BASIC TIMING REGISTER3
Offset: 0x054
Register Name: TCON0_BASIC3_REG
Bit
Read/
Write
Default/
Hex
Description
31:26
/
/
/
25:16
R/W
0
HSPW
Thspw = (HSPW+1) * Tdclk
Note: HT> (HSPW+1)
15:10
/
/
/
9:0
R/W
0
VSPW
Tvspw = (VSPW+1) * Thsync
Note: VT/2 > (VSPW+1)
5.1.4.10. TCON0 HV PANEL INTERFACE REGISTER
Offset: 0x058
Register Name: TCON0_HV_IF_REG
Bit
Read/
Write
Default/
Hex
Description
31
R/W
0
HV_Mode
0: 24bit parallel mode
1: 8bit serial mode
30
R/W
0
Serial_Mode
0: 8bit/3cycle RGB serial mode(RGB888)
1: 8bit/2cycle YUV serial mode(CCIR656)
29:28
/
/
/
27:26
R/W
0
RGB888_SM0