Allwinner A20 - Page 416

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 416 / 812
Offset: 0x058
Register Name: TCON0_HV_IF_REG
Bit
Read/
Write
Default/
Hex
Description
serial RGB888 mode Output sequence at odd lines of the panel
(line 1, 3, 5, 7…)
00: R-->G-->B
01: B-->R-->G
10: G-->B-->R
11: R-->G-->B
25:24
R/W
0
RGB888_SM1
serial RGB888 mode Output sequence at even lines of the panel
(line 2, 4, 6, 8…)
00: R-->G-->B
01: B-->R-->G
10: G-->B-->R
11: R-->G-->B
23:22
R/W
0
YUV_SM
serial YUV mode Output sequence 2-pixel-pair of every scan line
00: YUYV
01: YVYU
10: UYVY
11: VYUY
21:20
R/W
0
YUV EAV/SAV F line delay
0:F toggle right after active video line
1:delay 2 line(CCIR NTSC)
2:delay 3 line(CCIR PAL)
3:reserved
19:0
/
/
/
5.1.4.11. TCON0 CPU PANEL INTERFACE REGISTER
Offset: 0x060
Register Name: TCON0_CPU_IF_REG
Bit
Read/
Write
Default/
Hex
Description
31:29
R/W
0
CPU_MOD
000: 18bit/256K mode
001: 16bit mode0