Allwinner A20 - Page 418

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 418 / 812
Bit
Read/
Write
Default/
Hex
Description
31:24
/
/
/
23:0
W
0
Data_Wr
data write on 8080 bus, launch a write operation on 8080 bus
5.1.4.13. TCON0 CPU PANEL READ DATA REGISTER0
Offset: 0x068
Register Name: TCON0_CPU_RD0_REG
Bit
Read/
Write
Default/
Hex
Description
31:24
/
/
/
23:0
R
/
Data_Rd0
data read on 8080 bus, launch a new read operation on 8080 bus
5.1.4.14. TCON0 CPU PANEL READ DATA REGISTER1
Offset: 0x06C
Register Name: TCON0_CPU_RD1_REG
Bit
Read/
Write
Default/
Hex
Description
31:24
/
/
/
23:0
R
/
Data_Rd1
data read on 8080 bus, without a new read operation on 8080 bus
5.1.4.15. TCON0 TTL PANEL TIMING REGISTER 0
Offset: 0x070
Register Name: TCON0_TTL0_REG
Bit
Read/
Write
Default/
Hex
Description
31:20
R/W
0
STVH
STV high plus width (in dclk)
Tstvh = (STVH +1) * Tdclk
Note: STV has a period of one frame