Allwinner A20 - Page 420

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 420 / 812
Offset: 0x078
Register Name: TCON0_TTL2_REG
Bit
Read/
Write
Default/
Hex
Description
Toevh = (OEVH + 1) * Tdclk
9:0
R/W
0
OEVD
VSYNC –OEV delay time(in dclk)
Toevd = OEVD * Tdclk
5.1.4.18. TCON0 TTL PANEL TIMING REGISTER3
Offset: 0x07C
Register Name: TCON0_TTL3_REG
Bit
Read/
Write
Default/
Hex
Description
31:26
R/W
0
STHH
STH high plus time(in dclk)
Tsthh = (STHH+1) * Tdclk
Note: STH has a period of one line
25:16
R/W
0
STHD
HSYNC-STH delay time(in dclk)
Tsthd = STHD * Tdclk
15:10
R/W
0
OEHH
OEH high plus time(in dclk)
Tldh = (OEHH+1) * Tdclk
9:0
R/W
0
OEHD
HSYNC -OEH delay time(in dclk)
Tldd = OEHD * Tdclk
5.1.4.19. TCON0 TTL PANEL TIMING REGISTER3
Offset: 0x080
Register Name: TCON0_TTL4_REG
Bit
Read/
Write
Default/
Hex
Description
31:24
/
/
/
23
R/W
0
Output_Data_Rate