Allwinner A20 - Page 47

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 47 / 812
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
PLL7_Enable.
0: Disable, 1: Enable.
In the integer mode, The PLL7 output=3MHz*M.
In the fractional mode, the PLL7 output is select by bit 14.
The PLL7 output range is 27MHz~381MHz.
30:16
/
/
/.
15
R/W
0x1
PLL7_MODE_SEL.
PLL7 mode select.
0: fractional mode, 1: integer mode.
14
R/W
0x1
PLL7_FRAC_SET.
PLL7 fractional setting.
0: 270MHz, 1: 297MHz.
13:7
/
/
/.
6:0
R/W
0x63
PLL7_FACTOR_M.
PLL7 Factor M.
The range is from 9 to 127.
1.5.4.12. PLL1-TUNING2(DEFAULT: 0X00000000)
Offset: 0x38
Register Name: PLL1_TUN2_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SIG_DELT_PAT_EN.
Sigma-delta pattern enable.
30:29
R/W
0x0
SPR_FREQ_MODE.
Spread Frequency Mode.
00: DC=0
01: DC=1
10: Triangular
11: awmode
28:20
R/W
0x0
WAVE_STEP.
Wave step.
19
/
/
/
18:17
R/W
0x0
FREQ.