Allwinner A20 - Page 48

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 48 / 812
Offset: 0x38
Register Name: PLL1_TUN2_REG
Bit
Read/
Write
Default/Hex
Description
Frequency.
00: 31.5KHz
01: 32KHz
10: 32.5KHz
11: 33KHz
16:0
R/W
0x0
WAVE_BOT.
Wave Bottom.
1.5.4.13. PLL5-TUNING2(DEFAULT: 0X00000000)
Offset: 0x3C
Register Name: PLL5_TUN2_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SIG_DELT_PAT_EN.
Sigma-delta pattern enable.
30:29
R/W
0x0
SPR_FREQ_MODE.
Spread Frequency Mode.
00: DC=0
01: DC=1
10: Triangular
11: awmode
28:20
R/W
0x0
WAVE_STEP.
Wave step.
19
/
/
/
18:17
R/W
0x0
FREQ.
Frequency.
00: 31.5KHz
01: 32KHz
10: 32.5KHz
11: 33KHz
16:0
R/W
0x0
WAVE_BOT.
Wave Bottom.