Allwinner A20 - Page 471

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 471 / 812
Offset: 0x504
Register name: DDC_Slave_Addr
Bits
Read
/Write
Default
/Hex
Description
23:16
R/W
0
Addr1
DDC address for E-DDC read operation
15:8
R/W
0
Addr2
Offset address to be sent for non-implicit read
｡｢
write operation.
6:0
R/W
0
Addr3
Slave Address
5.2.4.35. DDC INTERRUPT MASK REGISTER
Offset: 0x508
Register name: DDC_Int_Mask
Bits
Read
/Write
Default
/Hex
Description
31:6
/
/
reserved
7
R/W
0
Illegal_FIFO_Op_Int_Msk
0: disable
1: enable
Illegal FIFO operation interrupt mask
6
R/W
0
DDC_FIFO_Underflow_Int_Mask
0: not underflow
1: underflow
DDC FIFO underflow interrupt mask
This bit is set when FIFO underflow in read operation.
Write 1 to this bit will clear it
5
R/W
0
DDC_FIFO_Overflow_Int_Mask
0: not overflow
1: overflow
This bit is set when FIFO overflow in write operation.
Write 1 to this bit will clear it
4
R
0
DDC_FIFO_Request_Int_En
This bit is set when FIFO level is below the TX trigger thresh in
write operation, or when FIFO level is above the RX trigger thresh
in read operation, write 1 to this bit will clear it.
Note: this bit can only be set when correct FIFO direction is set.