Allwinner A20 - Page 472

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 472 / 812
Offset: 0x508
Register name: DDC_Int_Mask
Bits
Read
/Write
Default
/Hex
Description
3
R/W
0
DDC_Arbitration_Error_Int_Mask
0: disable
1: enable
2
R/W
0
DDC_ACK_Error_Int_Mask
0: disable
1: enable
1
R/W
0
DDC_Bus_Error_Int_Mask
0: disable
1: enable
0
R/W
0
DDC_Transfer_Complete_Int_Mask
0: disable
1: enable
5.2.4.36. DDC INTERRUPT STATUS REGISTER:
Offset: 0x50C
Register name: DDC_Int_Status
Bits
Read
/Write
Default
/Hex
Description
31:8
/
/
reserved
8
R
0
Interrupt_Clear_Status
0: Interrupt have be cleared
1: Interrupt clear is in process
Note : When clear interrupt, must check this bit for clear complete
7
R/W
0
Illegal_FIFO_operation_interrupt_status_bit
6
R/W
0
DDC_RX FIFO_Underflow_Interrupt_Status_Bit
0: not underflow
1: underflow
This bit is set when FIFO underflow
Write 1 to this bit will clear it
5
R/W
0
DDC_TX FIFO_Overflow_Interrupt_Status_Bit
0: not overflow
1: overflow