Allwinner A20 - Page 474

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 474 / 812
5.2.4.38. DDC FIFO STATUS REGISTER
Offset: 0x514
Register name: DDC_FIFO_Status
Bits
Read
/Write
Default
/Hex
Description
31:8
/
/
reserved
7
R
0
FIFO_Request_Ready
FIFO level is below FIFO_TX_TRIGGER_THRESH in write mode
or is above FIFO_RX_TRIGGER_THRESH in read mode,
6
R
0
FIFO_FULL
5
R
1
FIFO_EMPTY
4:0
R
0
FIFO_LEVEL
5.2.4.39. DDC FIFO ACCESS REGISTER
Offset: 0x518
Register name: DDC_FIFO_Access
Bits
Read
/Write
Default
/Hex
Description
31:0
R/W
0
DDC_FIFO_Access_Register
Write only in DDC write operation, and read only in DDC read
operation
5.2.4.40. DDC ACCESS DATA BYTE NUMBER
Offset: 0x51C
Register name: DDC_Byte_Counter
Bits
Read
/Write
Default
/Hex
Description
31:10
/
/
Reserved
9:0
R/W
0
DDC_Access_Data_Byte_Number