Allwinner A20 - Page 480

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 480 / 812
Register Name
Offset
Description
DEFE_DI_SPATCOMP_REG
0x00B0
DEFE De-interlacing Spatial Compare
Register
DEFE_DI_BURSTLEN_REG
0x00B4
DEFE De-interlacing DMA Burst Length
Register
DEFE_DI_PRELUMA_REG
0x00B8
DEFE De-interlacing Pre-Frame Luma
Address Register
DEFE_DI_TILEFLAG_REG
0x00BC
DEFE De-interlacing Tile Flag Address
Register
DEFE_DI_FLAGLINESTRD_R
EG
0x00C0
DEFE De-interlacing Tile Flag LineStride
Register
DEFE_WB_LINESTRD_EN_R
EG
0x00D0
DEFE Write Back Line Stride Enable Register
DEFE_WB_LINESTRD0_REG
0x00D4
DEFE Write Back Channel 3 Line Stride
Register
DEFE_WB_LINESTRD1_REG
0x00D8
DEFE Write Back Channel 4 Line Stride
Register
DEFE_WB_LINESTRD2_REG
0x00DC
DEFE Write Back Channel 5 Line Stride
Register
DEFE_3D_CTRL_REG
0x00E0
DEFE 3D Mode Control Register
DEFE_3D_BUF_ADDR0_REG
0x00E4
DEFE 3D Channel 0 Buffer Address Register
DEFE_3D_BUF_ADDR1_REG
0x00E8
DEFE 3D Channel 1 Buffer Address Register
DEFE_3D_BUF_ADDR2_REG
0x00EC
DEFE 3D Channel 2 Buffer Address Register
DEFE_3D_TB_OFF0_REG
0x00F0
DEFE 3D Channel 0 Tile-Based Offset
Register
DEFE_3D_TB_OFF1_REG
0x00F4
DEFE 3D Channel 1 Tile-Based Offset
Register
DEFE_3D_TB_OFF2_REG
0x00F8
DEFE 3D Channel 2 Tile-Based Offset
Register
DEFE_CH0_INSIZE_REG
0x0100
DEFE Channel 0 Input Size Register
DEFE_CH0_OUTSIZE_REG
0x0104
DEFE Channel 0 Output Size Register
DEFE_CH0_HORZFACT_RE
G
0x0108
DEFE Channel 0 Horizontal Factor Register
DEFE_CH0_VERTFACT_RE
G
0x010C
DEFE Channel 0 Vertical factor Register
DEFE_CH0_HORZPHASE_R
EG
0x0110
DEFE Channel 0 Horizontal Initial Phase
Register
DEFE_CH0_VERTPHASE0_R
EG
0x0114
DEFE Channel 0 Vertical Initial Phase 0
Register