Allwinner A20 - Page 495

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 495 / 812
Offset: 0x5C
Register Name: DEFE_OUTPUT_FMT_REG
Bit
Read/
Write
Default/
Hex
Description
When output interlace enable, scaler selects YUV initial phase
according to LCD field signal
3
/
/
/
2:0
R/W
0x0
DATA_FMT
Data format
000: planar RGB888 conversion data format
001: interleaved BGRA8888 conversion data format(A component
always be pad 0xff)
010: interleaved ARGB8888 conversion data format(A component
always be pad 0xff)
100: planar YUV 444
101: planar YUV 420(only support YUV input and not interleaved
mode)
110: planar YUV 422(only support YUV input)
111: planar YUV 411(only support YUV input)
Other: reserved
5.3.4.21. DEFE_INT_EN_REG
Offset: 0x60
Register Name: DEFE_INT_EN_REG
Bit
Read/
Write
Default/H
ex
Description
31:11
/
/
/
10
R/W
0x0
REG_LOAD_EN
Register ready load interrupt enable
9
R/W
0x0
LINE_EN
Line interrupt enable
8
/
/
/
7
R/W
0x0
WB_EN
Write-back end interrupt enable
0: Disable
1: Enable
6:0
/
/
/