Allwinner A20 - Page 496

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 496 / 812
5.3.4.22. DEFE_INT_STATUS_REG
Offset: 0x64
Register Name: DEFE_INT_STATUS_REG
Bit
Read/
Write
Default/H
ex
Description
31:11
/
/
/
10
R/W
0x0
REG_LOAD_STATUS
Register ready load interrupt status
9
R/W
0x0
LINE_STATUS
Line interrupt status
8
/
/
/
7
R/W
0x0
WB_STATUS
Write-back end interrupt status
6:0
/
/
/
5.3.4.23. DEFE_STATUS_REG
Offset: 0x68
Register Name: DEFE_STATUS_REG
Bit
Read/
Write
Default/
Hex
Description
31:29
/
/
/
28:16
R
0x0
LINE_ON_SYNC
Line number(when sync reached)
15
R/W
0x0
WB_ERR_SYNC
Sync reach flag when capture in process
14
R/W
0x0
WB_ERR_LOSEDATA
Lose data flag when capture in process
13
/
/
/
12
R
0x0
WB_ERR_STATUS
write-back error status
0: valid write back
1: un-valid write back
This bit is cleared through write 0 to reset/start bit in frame control