Allwinner A20 - Page 497

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 497 / 812
Offset: 0x68
Register Name: DEFE_STATUS_REG
Bit
Read/
Write
Default/
Hex
Description
register
11:6
/
/
/
5
R
0x0
LCD_FIELD
LCD field status
0: top field
1: bottom field
4
R
0x0
DRAM_STATUS
Access dram status
0: idle
1: busy
This flag indicates whether scaler is accessing dram
3
/
/
/
2
R
0x0
CFG_PENDING
Register configuration pending
0: no pending
1: configuration pending
This bit indicates the registers for the next frame has been
configured. This bit will be set when configuration ready bit is set
and this bit will be cleared when a new frame process begin.
1
R
0x0
WB_STATUS
Write-back process status
0: write-back end or write-back disable
1: write-back in process
This flag indicates that a full frame has not been written back to
memory. The bit will be set when write-back enable bit is set, and
be cleared when write-back process end.
0
R
0x0
FRM_BUSY
Frame busy.
This flag indicates that the frame is being processed.
The bit will be set when frame process reset & start is set, and be
cleared when frame process reset or disabled.