Allwinner A20 - Page 50

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 50 / 812
Offset: 0x50
Register Name: OSC24M_CFG_REG
Bit
Read/
Write
Default/Hex
Description
If the key field value is 0xA7, the bit[23:16] can be modified.
23:17
/
/
/
16
R/W
0x1
LDO_EN.
LDO Enable.
0: Disable, 1: Enable.
15
R/W
0x1
PLL_BIAS_EN.
PLL Bias Enable.
0: disable,
1: enable.
14:2
/
/
/
1
R/W
0x1
OSC24M_GSM.
OSC24M GSM.
0
R/W
0x1
OSC24M_EN.
OSC24M Enable.
0: Disable, 1: Enable.
1.5.4.16. CPU/AHB/APB0 CLOCK RATIO(DEFAULT: 0X00010010)
Offset: 0x54
Register Name: CPU_AHB_APB0_CFG_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
DVFS_START.
DVFS start. Set 1 to this bit will start the DVFS.
It will be cleared automatically after the DVFS is finished.
30:18
/
/
/
17:16
R/W
0x1
CPU_CLK_SRC_SEL.
CPU0/1 Clock Source Select.
00: LOSC
01: OSC24M
10: PLL1
11: 200MHz(source from the PLL6).
If the clock source is changed, at most to wait for 8 present
running clock cycles.