Allwinner A20 - Page 51

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 51 / 812
Offset: 0x54
Register Name: CPU_AHB_APB0_CFG_REG
Bit
Read/
Write
Default/Hex
Description
15:13
/
/
/
12:11
R/W
0x0
10
/
/
/
9:8
R/W
0x0
APB0_CLK_RATIO.
APB0 Clock divide ratio. APB0 clock source is AHB clock.
00: /2
01: /2
10: /4
11: /8
7:6
R/W
0x0
AHB_CLK_SRC_SEL.
00: AXI
01: PLL6/2
10: PLL6
11: /
5:4
R/W
0x1
AHB_CLK_DIV_RATIO.
AHB Clock divide ratio.
00: /1
01: /2
10: /4
11: /8
3:2
/
/
ATB_APB_CLK_DIV.
00: /1
01: /2
1x: /4
Note: System ATB/APB clock source is CPU clock source.
1:0
R/W
0x0
AXI_CLK_DIV_RATIO.
AXI Clock divide ratio.
AXI Clock source is CPU clock.
00: /1
01: /2
10: /3
11: /4