Allwinner A20 - Page 604

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 604 / 812
Offset: 0x1C
Register Name: SPI_CCTL
Default Value: 0x0000_0002
Bit
Read/Write
Default
Description
SPI_SCLK is determined according to the following equation:
SPI_CLK = AHB_CLK / 2^(n+1).
7:0
R/W
0x2
CDR2
Clock Divide Rate 2 (Master Mode Only)
The SPI_SCLK is determined according to the following
equation: SPI_CLK = AHB_CLK / (2*(n + 1)).
6.3.4.9. SPI BURST COUNTER REGISTER
Offset: 0x20
Register Name: SPI_BC
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:24
/
/
/
23:0
R/W
0
BC
Burst Counter
In master mode, this field specifies the total burst number
when SMC is 1.
0: 0 burst
1: 1 burst
…
N: N bursts
6.3.4.10. SPI TRANSMIT COUNTER REGISTER
Offset: 0x24
Register Name: SPI_TC
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:24
/
/
/
23:0
R/W
0
WTC
Write Transmit Counter
In master mode, this field specifies the burst number that
should be sent to TXFIFO before automatically sending