A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 620 / 812
Register Name: UART_LSR
Default Value: 0x0000_0060
is cleared when the CPU writes to the TX Holding Register.
If the FIFOs are enabled, this bit is set to “1” whenever the TX
FIFO is empty and it is cleared when at least one byte is
written
to the TX FIFO.
BI
Break Interrupt
This is used to indicate the detection of a break sequence on
the serial input data.
If in UART mode (SIR_MODE == Disabled), it is set whenever
the serial input, sin, is held in a logic ‘0’ state for longer than
the sum of start time + data bits + parity + stop bits.
If in infrared mode (SIR_MODE == Enabled), it is set
whenever the serial input, sir_in, is continuously pulsed to
logic ‘0’ for longer than the sum of start time + data bits +
parity + stop bits. A break condition on serial input causes one
and only one character, consisting of all zeros, to be received
by the UART.
In the FIFO mode, the character associated with the break
condition is carried through the FIFO and is revealed when the
character is at the top of the FIFO. Reading the LSR clears the
BI bit. In the non-FIFO mode, the BI indication occurs
immediately and persists until the LSR is read.
FE
Framing Error
This is used to indicate the occurrence of a framing error in the
receiver. A framing error occurs when the receiver does not
detect a valid
STOP bit in the received data.
In the FIFO mode, since the framing error is associated with a
character received, it is revealed when the character with the
framing error is at the top of the FIFO. When a framing error
occurs, the UART tries to resynchronize. It does this by
assuming that the error was due to the start bit of the next
character and then continues receiving the other bit i.e. data,
and/or parity and stop. It should be noted that the Framing
Error (FE) bit (LSR[3]) is set if a break interrupt has
occurred, as indicated by Break Interrupt (BI) bit (LSR[4]).
0: no framing error
1:framing error
Reading the LSR clears the FE bit.
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