Allwinner A20 - Page 621

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 621 / 812
Offset: 0x14
Register Name: UART_LSR
Default Value: 0x0000_0060
Bit
Read/Write
Default
Description
2
R
0
PE
Parity Error
This is used to indicate the occurrence of a parity error in the
receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the
FIFO mode, since the parity error is associated with a
character received, it is revealed when the character with the
parity error arrives at the top of the FIFO. It should be noted
that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt
has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]).
0: no parity error
1: parity error
Reading the LSR clears the PE bit.
1
R
0
OE
Overrun Error
This occurs if a new data character was received before the
previous data was read. In the non-FIFO mode, the OE bit is
set when a new character arrives in the receiver before the
previous character was read from the RBR. When this
happens, the data in the RBR is overwritten. In the FIFO
mode, an overrun error occurs when the FIFO is full and a new
character arrives at the receiver. The data in the FIFO is
retained and the data in the receive shift register is lost.
0: no overrun error
1: overrun error
Reading the LSR clears the OE bit.
0
R
0
DR
Data Ready
This is used to indicate that the receiver contains at least one
character in the RBR or the receiver FIFO.
0: no data ready
1: data ready
This bit is cleared when the RBR is read in non-FIFO mode, or
when the receiver FIFO is empty, in FIFO mode.