Allwinner A20 - Page 622

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 622 / 812
6.4.4.11. UART MODEM STATUS REGISTER
Offset: 0x18
Register Name: UART_MSR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:8
/
/
/
7
R
0
DCD
Line State of Data Carrier Detect
This is used to indicate the current state of the modem control
line dcd_n. This bit is the complement of dcd_n. When the
Data Carrier Detect input (dcd_n) is asserted it is an indication
that the carrier has been detected by the modem or data set.
0: dcd_n input is de-asserted (logic 1)
1: dcd_n input is asserted (logic 0)
6
R
0
RI
Line State of Ring Indicator
This is used to indicate the current state of the modem control
line ri_n. This bit is the complement of ri_n. When the Ring
Indicator input (ri_n) is asserted it is an indication that a
telephone ringing signal has been received by the modem or
data set.
0: ri_n input is de-asserted (logic 1)
1: ri_n input is asserted (logic 0)
5
R
0
DSR
Line State of Data Set Ready
This is used to indicate the current state of the modem control
line dsr_n. This bit is the complement of dsr_n. When the Data
Set Ready input (dsr_n) is asserted it is an indication that the
modem or data set is ready to establish communications with
UART.
0: dsr_n input is de-asserted (logic 1)
1: dsr_n input is asserted (logic 0)
In Loopback Mode (MCR[4] set to one), DSR is the same as
MCR[0] (DTR).
4
R
0
CTS
Line State of Clear To Send
This is used to indicate the current state of the modem control
line cts_n. This bit is the complement of cts_n. When the Clear
to Send input (cts_n) is asserted it is an indication that the
modem or data set is ready to exchange data with UART.
0: cts_n input is de-asserted (logic 1)
1: cts_n input is asserted (logic 0)