Allwinner A20 - Page 623

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 623 / 812
Offset: 0x18
Register Name: UART_MSR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1]
(RTS).
3
R
0
DDCD
Delta Data Carrier Detect
This is used to indicate that the modem control line dcd_n has
changed since the last time the MSR was read.
0: no change on dcd_n since last read of MSR
1: change on dcd_n since last read of MSR
Reading the MSR clears the DDCD bit.
Note: Ff the DDCD bit is not set and the dcd_n signal is
asserted (low) and a reset occurs (software or otherwise), then
the DDCD bit is set when the reset is removed if the dcd_n
signal remains asserted.
2
R
0
TERI
Trailing Edge Ring Indicator
This is used to indicate that a change on the input ri_n (from
an active-low to an inactive-high state) has occurred since the
last time
the MSR was read.
0: no change on ri_n since last read of MSR
1: change on ri_n since last read of MSR
Reading the MSR clears the TERI bit.
1
R
0
DDSR
Delta Data Set Ready
This is used to indicate that the modem control line dsr_n has
changed since the last time the MSR was read.
0: no change on dsr_n since last read of MSR
1: change on dsr_n since last read of MSR
Reading the MSR clears the DDSR bit. In Loopback Mode
(MCR[4] = 1), DDSR reflects changes on MCR[0] (DTR).
Note: If the DDSR bit is not set and the dsr_n signal is
asserted (low) and a reset occurs (software or otherwise), then
the DDSR bit is set when the reset is removed if the dsr_n
signal remains asserted.
0
R
0
DCTS
Delta Clear to Send
This is used to indicate that the modem control line cts_n has
changed since the last time the MSR was read.