Allwinner A20 - Page 636

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 636 / 812
Offset: 0x0008
Register Name: PS2_LCTL
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
Acknowledge Error Interrupt Enable
1
R/W
0
PARERR_IEN
Parity Error Interrupt Enable
0
R/W
0
RXDTO_IEN
RX Data Timeout Interrupt Enable
6.5.5.4. PS2 LINE STATUS REGISTER
Offset: 0x000C
Register Name: PS2_LSTS
Default Value: 0x0003_0000
Bit
Read/Write
Default
Description
31:20
/
/
/
19
R
0
TX_BUSY
Transmit Busy
0 – PS2 Module Transmit Engine is Idle.
1 – PS2 Module is currently sending data.
Note: This bit can be cleared by writing ‘1’, writing ‘0’ has no
effect.
18
R
0
RX_BUSY
Receive Busy
0 –PS2 Module Receive Engine is Idle.
1 –PS2 Module is currently receiving data.
Note: This bit can be cleared by writing ‘1’, writing ‘0’ has no
effect.
17
R
1
LS_DATA
Line State of DATA. Invalid before BUS_EN set.
16
R
1
LS_CLK
Line State of CLOCK. Invalid before BUS_EN set.
15:9
/
/
/
8
R/W
0
TX_DTO
Transmit Data Timeout
Timers include: