Allwinner A20 - Page 664

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Offset: 0x10
Register Name: USBCMD
Default Value: 0x00080000(0x00080B00 if Asynchronous
Schedule Park Capability is a one)
Bit
Read/Write
Default
Description
0x04
4 micro-frame
0x08
8 micro-frame(default, equates to 1 ms)
0x10
16 micro-frame(2ms)
0x20
32 micro-frame(4ms)
0x40
64 micro-frame(8ms)
Any other value in this register yields undefined results.
The default value in this field is 0x08 .
Software modifications to this bit while HC Halted bit is equal
to zero results in undefined behavior.
15:12
/
0
Reserved
These bits are reserved and should be set to zero.
11
R/W or R
0
ASPME
Asynchronous Schedule Park Mode Enable(OPTIONAL)
If the Asynchronous Park Capability bit in the HCCPARAMS
register is a one, then this bit defaults to a 1 and is R/W.
Otherwise the bit must be a zero and is Read Only. Software
uses this bit to enable or disable Park mode. When this bit is
one, Park mode is enabled. When this bit is zero, Park mode
is disabled.
10
/
0
Reserved
These bits are reserved and should be set to zero.
9:8
R/W or R
0
ASPMC
Asynchronous Schedule Park Mode Count(OPTIONAL)
Asynchronous Park Capability bit in the HCCPARAMS
register is a one,
Then this field defaults to 0x3 and is W/R. Otherwise it
defaults to zero and is R. It contains a count of the number of
successive transactions the host controller is allowed to
execute from a high-speed queue head on the Asynchronous
schedule before continuing traversal of the Asynchronous
schedule.
Valid value are 0x1 to 0x3.Software must not write a zero to
this bit when Park Mode Enable is a one as it will result in
undefined behavior.
7
R/W
0
LHCR
Light Host Controller Reset(OPTIONAL)