A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 665 / 812
Register Name: USBCMD
Default Value: 0x00080000(0x00080B00 if Asynchronous
Schedule Park Capability is a one)
This control bit is not required.
If implemented, it allows the driver to reset the EHCI
controller without affecting the state of the ports or
relationship to the companion host controllers. For example,
the PORSTC registers should not be reset to their default
values and the CF bit setting should not go to zero (retaining
port ownership relationships).
A host software read of this bit as zero indicates the Light
Host Controller Reset has completed and it si safe for
software to re-initialize the host controller. A host software
read of this bit as a one indicates the Light Host
IAAD
Interrupt on Async Advance Doorbell
This bit is used as a doorbell by software to tell the host
controller to issue an interrupt the next time it advances
asynchronous schedule. Software must write a 1 to this bit to
ring the doorbell.
When the host controller has evicted all appropriate cached
schedule state, it sets the Interrupt on Async Advance status
bit in the USBSTS. if the Interrupt on Async Advance Enable
bit in the USBINTR register is a one then the host controller
will assert an interrupt at the next interrupt threshold.
The host controller sets this bit to a zero after it has set the
Interrupt on Async Advance status bit in the USBSTS register
to a one.
Software should not write a one to this bit when the
asynchronous schedule is disabled. Doing so will yield
undefined results.
ASE
Asynchronous Schedule Enable
This bit controls whether the host controller skips processing
the Asynchronous Schedule. Values mean:
Do not process the Asynchronous Schedule.
Use the ASYNLISTADDR register to access the
Asynchronous Schedule.
The default value of this field is ‘0b’.
PSE
Periodic Schedule Enable
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