Allwinner A20 - Page 667

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 667 / 812
Offset: 0x10
Register Name: USBCMD
Default Value: 0x00080000(0x00080B00 if Asynchronous
Schedule Park Capability is a one)
Bit
Read/Write
Default
Description
the CHEI Specification in order to return the host controller to
an operational state.
This bit is set to zero by the Host Controller when the reset
process is complete. Software cannot terminate the reset
process early by writing a zero to this register.
Software should not set this bit to a one when the HC Halted
bit in the USBSTS register is a zero. Attempting to reset an
actively running host controller will result in undefined
behavior.
0
R/W
0
RS
Run/Stop
When set to a 1, the Host Controller proceeds with execution
of the schedule. When set to 0, the Host Controller completes
the current and any actively pipelined transactions on the
USB and then halts. The Host Controller must halt within 16
micro-frames after software clears this bit.
The HC Halted bit indicates when the Host Controller has
finished its pending pipelined transactions and has entered
the stopped state.
Software must not write a one to this field unless the Host
Controller is in the Halt State.
The default value is 0x0.
6.8.5.7. EHCI USB STATUS REGISTER
Offset: 0x14
Register Name: USBSTS
Default Value: 0x00001000
Bit
Read/Write
Default
Description
31:16
/
0
Reserved
These bits are reserved and should be set to zero.
15
R
0
ASS
Asynchronous Schedule Status
The bit reports the current real status of Asynchronous
Schedule. If this bit is a zero then the status of the
Asynchronous Schedule is disabled. If this bit is a one then the
status of the Asynchronous Schedule is enabled. The Host
Controller is not required to immediately disable or enable the