Allwinner A20 - Page 672

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 672 / 812
Offset: 0x24
Register Name: PERIODICLISTBASE
Default Value: Undefined
Bit
Read/Write
Default
Description
respectively.
This register contains the beginning address of the Periodic
Frame List in the system memory.
System software loads this register prior to starting the
schedule execution by the Host Controller. The memory
structure referenced by this physical memory pointer is
assumed to be 4-K byte aligned. The contents of this register
are combined with the Frame Index Register (FRINDEX) to
enable the Host Controller to step through the Periodic Frame
List in sequence.
11:0
/
Reserved
Must be written as 0x0 during runtime, the values of these bits
are undefined.
Note: Writes must be Dword Writes.
6.8.5.11. EHCI CURRENT ASYNCHRONOUS LIST ADDRESS REGISTER
Offset: 0x28
Register Name: ASYNCLISTADDR
Default Value: Undefined
Bit
Read/Write
Default
Description
31:5
R/W
LP
Link Pointer (LP)
This field contains the address of the next asynchronous
queue head to be executed.
These bits correspond to memory address signals [31:5],
respectively.
4:0
/
/
Reserved
These bits are reserved and their value has no effect on
operation.
Bits in this field cannot be modified by system software and will
always return a zero when read.
Note: Write must be DWord Writes.