Allwinner A20 - Page 673

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6.8.5.12. EHCI CONFIGURE FLAG REGISTER
Offset: 0x50
Register Name: CONFIGFLAG
Default Value: 0x00000000
Bit
Read/Write
Default
Description
31:1
/
0
Reserved
These bits are reserved and should be set to zero.
0
R/W
0
CF
Configure Flag(CF)
Host software sets this bit as the last action in its process of
configuring the Host Controller. This bit controls the default
port-routing control logic as follow:
Valu
e
Meaning
0
Port routing control logic default-routs each port to an
implementation dependent classic host controller.
1
Port routing control logic default-routs all ports to this
host controller.
The default value of this field is ‘0’.
Note: This register is not use in the normal implementation.
6.8.5.13. EHCI PORT STATUS AND CONTROL REGISTER
Offset: 0x54
Register Name: PORTSC
Default Value: 0x00002000(w/PPC set to
one);0x00003000(w/PPC set to a zero)
Bit
Read/Write
Default
Description
31:22
/
0
Reserved
These bits are reserved for future use and should return a
value of zero when read.
21
R/W
0
WDE
Wake on Disconnect Enable(WKDSCNNT_E)
Writing this bit to a one enables the port to be sensitive to
device disconnects as wake-up events.
This field is zero if Port Power is zero.
The default value in this field is ‘0’.
20
R/W
0
WCE
Wake on Connect Enable(WKCNNT_E)
Writing this bit to a one enable the port to be sensitive to