Allwinner A20 - Page 753

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 753 / 812
Offset: TSG+0x00
Register Name: TSG_CSR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
23:10
/
/
/
9
R/W
0
TSGLBufMode
Loop Buffer Mode
When set to ‘1’, the TSG external buffer is in loop mode.
8
R/W
0
TSGSyncByteChkEn
Sync Byte Check Enable
Enable/ Disable check SYNC byte fro receiving new packet
0: Disable
1: Enable
If enable check SYNC byte and an error SYNC byte is
receiver, TS Generator would come into PAUSE state. If the
correspond interrupt is enable, the interrupt would happen.
7:3
/
/
/
2
R/W
0
TSGPauseBit
Pause Bit for TS Generator
Write ‘1’ to pause TS Generator. TS Generator would stop
fetch new data from DRAM. After finishing this operation, this
bit will clear to zero by hardware. In PAUSE state, write ‘1’ to
resume this state.
1
R/W
0
TSGStopBit
Stop Bit for TS Generator
Write ‘1’ to stop TS Generator. TS Generator would stop fetch
new data from DRAM. The data already in its FIFO should be
sent to TS filter. After finishing this operation, this bit will clear
to zero by hardware.
0
R/W
0
TSGStartBit
Start Bit for TS Generator
Write ‘1’ to start TS Generator. TS Generator would fetch data
from DRAM and generate SPI stream to TS filter. This bit will
clear to zero by hardware after TS Generator is running.
6.13.4.8. TSG PACKET PARAMETER REGISTER
Offset: TSG+0x04
Register Name: TSG_PPR
Default Value: 0x0000_0000