Allwinner A20 - Page 754

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 754 / 812
Bit
Read/Write
Default
Description
31:24
/
/
/
23:16
R/W
0x47
SyncByteVal
Sync Byte Value
This is the value of sync byte used in the TS Packet.
15:8
/
/
/
7
R/W
0
SyncBytePos
Sync Byte Position
0: the 1st byte position
1: the 5th byte position
Notes: This bit is only used for 192 bytes packet size.
6:2
/
/
/
1:0
R/W
0
PktSize
Packet Size
Byte Size for one TS packet
0: 188 bytes
1: 192 bytes
2: 204 bytes
3: Reserved
6.13.4.9. TSG INTERRUPT ENABLE AND STATUS REGISTER
Offset: TSG+0x08
Register Name: TSG_IESR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:20
/
/
/
19
R/W
0
TSGEndIE
TS Generator (TSG) End Interrupt Enable
0: Disable
1: Enable
If set this bit, the interrupt would assert to CPU when all data in
external DRAM are sent to TS PID filter.
18
R/W
0
TSGFFIE
TS Generator (TSG) Full Finish Interrupt Enable
0: Disable