Allwinner A20 - Page 755

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 755 / 812
Offset: TSG+0x08
Register Name: TSG_IESR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
1: Enable
17
R/W
0
TSGHFIE
TS Generator (TSG) Half Finish Interrupt Enable
0: Disable
1: Enable
16
R/W
0
TSGErrSyncByteIE
TS Generator (TSG) Error Sync Byte Interrupt Enable
0: Disable
1: Enable
15:4
/
/
/
3
R/W
0
TSGEndSts
TS Generator (TSG) End Status
Write ‘1’ to clear.
2
R/W
0
TSGFFSts
TS Generator (TSG) Full Finish Status
Write ‘1’ to clear.
1
R/W
0
TSGHFSts
TS Generator (TSG) Half Finish Status
Write ‘1’ to clear.
0
R/W
0
TSGErrSyncByteSts
TS Generator (TSG) Error Sync Byte Status
Write ‘1’ to clear.
6.13.4.10. TSG CLOCK CONTROL REGISTER
Offset: TSG+0x0c
Register Name: TSG_CCR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:16
R/W
0x0
TSGCDF_N
TSG Clock Divide Factor (N)
The Numerator part of TSG Clock Divisor Factor.
15:0
R/W
0x0
TSGCDF_D