Allwinner A20 - Page 777

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 777 / 812
Offset: 0x0008
Register Name: SCR_INTST
Default Value: 0x00000000
Bit
Read/Write
Default
Description
2
R/W
0
TXFIFOTHD
TX FIFO Threshold Interrupt. When enabled, this interrupt is
asserted if the number of bytes in TX FIFO is equal or less
than the TX FIFO threshold.
1
R/W
0
TXFIFOEMPTY
TX FIFO Empty Interrupt. When enabled, this interrupt is
asserted if the TX FIFO is emptied out.
0
R/W
0
TXFIFODONE
TX FIFO Done Interrupt. When enabled, this interrupt is
asserted after all bytes from TX FIFO ware transferred to the
Smart Card.
6.14.5.4. SMART CARD READER FIFO CONTROL AND STATUS REGISTER
Offset: 0x000c
Register Name: SCR_FCSR
Default Value: 0x00000000
Bit
Read/Write
Default
Description
31:11
/
/
/
10
R/W
0
RXFIFOFLUSH
Flush RX FIFO. RX FIFO is flushed, when ‘1’ is written to this
bit.
9
R
0
RXFIFOFULL
RX FIFO Full.
8
R
1
RXFIFOEMPTY
RX FIFO Empty.
7:3
/
/
/
2
R/W
0
TXFIFOFLUSH
Flush TX FIFO. TX FIFO is flushed, when ‘1’ is written to this
bit.
1
R
0
TXFIFOFULL
TX FIFO Full.
0
R
1
TXFIFOEMPTY
TX FIFO Empty.