Allwinner A20 - Page 781

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 781 / 812
6.14.5.10. SMART CARD READER LINE CONTROL REGISTER
This register provides direct access to smart card pads without serial interface assistance. You can
use this register feature with synchronous and any other non-ISO 7816 and non-EMV cards.
Offset: 0x0030
Register Name: SCR_PAD
Default Value: 0x00000000
Bit
Read/Write
Default
Description
31:8
/
/
/
7
R/W
0
DSCVPPPP
Direct Smart Card Vpp Pause/Prog. It provides direct access
to SCVPPPP output.
6
R/W
0
DSCVPPEN
Direct Smart Card Vpp Enable. It provides direct access to
SCVPPEN output.
5
R/W
0
AUTOADEAVPP
Automatic Vpp Handling. When high, it enables automatic
handling of DSVPPEN and DSVPPPP signals during
activation and deactivation sequence.
4
R/W
0
DSCVCC
Direct Smart Card VCC. When DIRACCPADS=’1’, the
DSCVCC bit provides direct access to SCVCC pad.
3
R/W
0
DSCRST
Direct Smart Card Clock. When DIRACCPADS=’1’, the
DSCRST bit provides direct access to SCRST pad.
2
R/W
0
DSCCLK
Direct Smart Card Clock. When DIRACCPADS=’1’, the
DSCCLK bit provides direct access to SCCLK pad.
1
R/W
0
DSCIO
Direct Smart Card Input/Output. When DIRACCPADS=’1’, the
DSCIO bit provides direct access to SCIO pad.
0
R/W
0
DIRACCPADS
Direct Access to Smart Card Pads. When high, it disables a
serial interface functionality and enables direct control of the
smart card pads using following 4 bits.
6.14.5.11. SMART CARD READER FIFO DATA REGISTER
Offset: 0x0100
Register Name: SCR_FIFO
Default Value: 0x00000000