ARM Cortex-A53 MPCore - Page 113

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-52
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Table 4-67 shows the SCTLR_EL1 bit assignments.
Table 4-67 SCTLR_EL1 bit assignments
Bits Name Function
[31:30] - Reserved,
RES0.
[29:28] - Reserved,
RES1.
[27] - Reserved,
RES0.
[26] UCI Enables EL0 access to the DC CVAU, DC CIVAC, DC CVAC and IC IVAU instructions in the AArch64
Execution state. The possible values are:
0 EL0 access disabled. This is the reset value.
1 EL0 access enabled.
[25] EE Exception endianness. The value of this bit controls the endianness for explicit data accesses at EL1. This
value also indicates the endianness of the translation table data for translation table lookups. The possible
values of this bit are:
0 Little-endian.
1 Big-endian.
The reset value of this bit is determined by the CFGEND configuration pin.
[24] E0E Endianness of explicit data access at EL0. The possible values are:
0 Explicit data accesses at EL0 are little-endian. This is reset value.
1 Explicit data accesses at EL0 are big-endian.
[23:22] - Reserved,
RES1.
[21] - Reserved,
RES0.
[20] - Reserved,
RES1.
[19] WXN Write permission implies Execute Never (XN). This bit can be used to require all memory regions with write
permissions to be treated as XN. The possible values are:
0 Regions with write permission are not forced XN. This is the reset value.
1 Regions with write permissions are forced XN.
[18] nTWE
WFE non-trapping. The possible values are:
0 A WFE instruction executed at EL0, that, if this bit was set to 1, would permit entry to a
low-power state, is trapped to EL1.
1 WFE instructions executed as normal. This is the reset value.
[17] - Reserved,
RES0.
[16] nTWI
WFI non-trapping. The possible values are:
0 A WFI instruction executed at EL0, that, if this bit was set to 1, would permit entry to a
low-power state, is trapped to EL1.
1 WFI instructions executed as normal. This is the reset value.
[15] UCT Enables EL0 access to the CTR_EL0 register in AArch64 Execution state. The possible values are:
0 Disables EL0 access to the CTR_EL0 register. This is the reset value.
1 Enables EL0 access to the CTR_EL0 register.
[14] DZE Enables access to the DC ZVA instruction at EL0. The possible values are:
0 Disables execution access to the DC ZVA instruction at EL0. The instruction is trapped to
EL1. This is the reset value.
1 Enables execution access to the DC ZVA instruction at EL0.
[13] - Reserved,
RES0.