System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-106
ID021414 Non-Confidential
4.3.64 L2 Control Register
The L2CTLR_EL1 characteristics are:
Purpose Provides
IMPLEMENTATION DEFINED control options for the L2 memory
system.
Usage constraints This register is accessible as follows:
L2CTLR_EL1 is writeable. However, all writes to this register are
ignored.
Configurations L2CTLR_EL1 is architecturally mapped to the AArch32 L2CTLR
register. See L2 Control Register on page 4-251.:
There is one L2CTLR_EL1 for the Cortex-A53 processor.
Attributes L2CTLR_EL1 is a 32-bit register.
Figure 4-58 shows the L2CTLR_EL1 bit assignments.
Figure 4-58 L2CTLR_EL1 bit assignments
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RWRWRWRW RW
31 026 25 24
Reserved
Number of cores
RES
0
23 1
L2 Data RAM input latency
22 21 20
Reserved
CPU Cache Protection
SCU- L2 cache protection
456
L2 Data RAM output latency
Reserved
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