ARM Cortex-A53 MPCore - Page 205

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-144
ID021414 Non-Confidential
4.4.13 c13 registers
Table 4-133 shows the 32-bit wide system registers you can access when the processor is in
AArch32 state and the value of CRn is c13.
4.4.14 c14 registers
Table 4-134 shows the CP15 system registers when the processor is in AArch32 state and the
value of CRn is c14. See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A
architecture profile for more information.
a. This is the reset value in non-secure state. In secure state, the reset value is 0x00000002.
Table 4-133 c13 register summary
CRn Op1 CRm Op2 Name Reset Description
c13 0 c0 0 FCSEIDR
0x00000000 FCSE Process ID Register on page 4-267
1 CONTEXTIDR UNK
Context ID Register
a
2 TPIDRURW UNK
User Read/Write Thread ID Register
a
3 TPIDRURO UNK
User Read-Only Thread ID Register
a
4 TPIDRPRW UNK
EL1 only Thread ID Register
a
4 c0 2 HTPIDR UNK
Hyp Software Thread ID Register
a
a. See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.
Table 4-134 c14 register summary
Op1 CRm Op2 Name Reset Description
0 c0 0 CNTFRQ UNK Timer Counter Frequency Register
c1 0 CNTKCTL
-
a
Timer Control Register
c2 0 CNTP_TVAL UNK Physical Timer TimerValue Register
1CNTP_CTL
-
b
Physical Timer Control Register
c3 0 CNTV_TVAL UNK Virtual Timer TimerValue Register
1 CNTV_CTL
-
b
Counter-timer Virtual Timer Control Register
c8 0 PMEVCNTR0 UNK Performance Monitor Event Count Registers
1 PMEVCNTR1 UNK
2 PMEVCNTR2 UNK
3 PMEVCNTR3 UNK
4 PMEVCNTR4 UNK
5 PMEVCNTR5 UNK