ARM Cortex-A53 MPCore - Page 206

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-145
ID021414 Non-Confidential
c12 0 PMEVTYPER0 UNK Performance Monitor Event Type Registers
1 PMEVTYPER1 UNK
2 PMEVTYPER2 UNK
3 PMEVTYPER3 UNK
4 PMEVTYPER4 UNK
5 PMEVTYPER5 UNK
c15 7 PMCCFILTR
0x00000000 Performance Monitor Cycle Count Filter Register.
4 c1 0 CNTHCTL
-
c
Timer Control Register (EL2)
c2 0 CNTHP_TVAL UNK Physical Timer TimerValue (EL2)
1 CNTHP_CTL
-
b
Physical Timer Control Register (EL2)
a. The reset value for bits[9:8, 2:0] is 0b00000 .
b. The reset value for bit[0] is 0.
c. The reset value for bit[2] is 0 and for bits[1:0] is
0b11 .
Table 4-134 c14 register summary (continued)
Op1 CRm Op2 Name Reset Description