System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-146
ID021414 Non-Confidential
4.4.15 c15 registers
Table 4-135 shows the 32-bit wide system registers you can access when the processor is in
AArch32 state and the value of CRn is c15.
Table 4-135 c15 register summary
Op1 CRm Op2 Name Reset Description
1c00L2ACTLR
0x80000000
a
L2 Auxiliary Control Register on page 4-267
c3 0 CBAR
-
b
Configuration Base Address Register on page 4-278
3 c0 0 CDBGDR0 UNK Cache Debug Data Register 0, see Direct access to internal memory on
page 6-13
1 CDBGDR1 UNK Cache Debug Data Register 1, see Direct access to internal memory on
page 6-13
2 CDBGDR2 UNK Cache Debug Data Register 2, see Direct access to internal memory on
page 6-13
3 CDBGDR3 UNK Cache Debug Data Register 3, see Direct access to internal memory on
page 6-13
c2 0 CDBGDCT UNK Cache Debug Data Cache Tag Read Operation Register, see Direct access
to internal memory on page 6-13
1 CDBGICT UNK Cache Debug Instruction Cache Tag Read Operation Register, see Direct
access to internal memory on page 6-13
c4 0 CDBGDCD UNK Cache Debug Cache Debug Data Cache Data Read Operation Register,
see Direct access to internal memory on page 6-13
1 CDBGICD UNK Cache Debug Instruction Cache Data Read Operation Register, see Direct
access to internal memory on page 6-13
2 CDBGTD UNK Cache Debug TLB Data Read Operation Register, see Direct access to
internal memory on page 6-13
a. This is the reset value for an ACE interface. For a CHI interface the reset value is
0x80004008
.
b. The reset value depends on the processor configuration.
To Next Page
Loading...
