System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-149
ID021414 Non-Confidential
4.4.18 AArch32 Virtual memory control registers
Table 4-138 shows the virtual memory control registers.
Table 4-138 Virtual memory control registers
Name CRn Op1 CRm Op2 Reset Width Description
SCTLR c1 0 c0 0
0x00C50838
a
32 bit System Control Register on page 4-191
TTBR0 c2 0 c0 0 UNK 32 bit
Translation Table Base Register 0, see the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A
architecture profile
- 0 c2 - 64 bit
TTBR1 0 c0 1 UNK 32 bit
Translation Table Base Register 1, see the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A
architecture profile
- 1 c2 - 64 bit
TTBCR 0 c0 2
0x00000000
b
32 bit Translation Table Base Control Register, see the
ARM
®
Architecture Reference Manual ARMv8, for
ARMv8-A architecture profile
DACR c3 0 c0 0 UNK 32 bit Domain Access Control Register on page 4-235
PRRR c10 0 c2 0 UNK 32 bit Primary Region Remap Register on page 4-256
MAIR0 0 UNK 32 bit Memory Attribute Indirection Registers 0 and 1 on
page 4-259
NMRR 1 UNK 32 bit Normal Memory Remap Register on page 4-262
MAIR1 1 UNK 32 bit Memory Attribute Indirection Registers 0 and 1 on
page 4-259
AMAIR0 c3 0
0x00000000
32 bit Auxiliary Memory Attribute Indirection Register 0 on
page 4-263
AMAIR1 1
0x00000000
32 bit Auxiliary Memory Attribute Indirection Register 1 on
page 4-263
CONTEXTIDR c13 0 c0 1 UNK 32 bit
Process ID Register, see the ARM
®
Architecture
Reference Manual ARMv8, for ARMv8-A architecture
profile
a. The reset value depends on inputs, CFGTE, CFGEND, and VINITHI. The value shown in Table 4-138 assumes these signals are set to
LOW.
b. The reset value is
0x00000000
for the Secure copy of the register. The reset value for the EAE bit of the Non-secure copy of the register is
0x0
. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.
To Next Page
Loading...
