ARM Cortex-A53 MPCore - Page 211

System Control
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4.4.19 AArch32 Fault handling registers
Table 4-139 shows the Fault handling registers in the AArch32 Execution state.
The Virtualization registers include additional fault handling registers. For more information see
AArch32 Virtualization registers on page 4-153.
4.4.20 AArch32 Other System control registers
Table 4-140 shows the other system registers.
4.4.21 AArch32 Address registers
Table 4-141 shows the address translation register and operations. See the ARM
®
Architecture
Reference Manual ARMv8, for ARMv8-A architecture profile for more information.
Table 4-139 Fault handling registers
Name CRn Op1 CRm Op2 Reset Description
DFSR c5 0 c0 0 UNK Data Fault Status Register on page 4-239
IFSR 1 UNK Instruction Fault Status Register on page 4-243
ADFSR c1 0
0x00000000 Auxiliary Data Fault Status Register on page 4-246
AIFSR 1
0x00000000 Auxiliary Instruction Fault Status Register on page 4-246
DFAR c6 0 c0 0 UNK
Data Fault Address Register, see the ARM
®
Architecture Reference
Manual ARMv8, for ARMv8-A architecture profile
IFAR 2 UNK
Instruction Fault Address Register, see the ARM
®
Architecture Reference
Manual ARMv8, for ARMv8-A architecture profile
Table 4-140 Other system registers
Name CRn Op1 CRm Op2 Reset Description
ACTLR c1 0 c0 1
0x00000000 Auxiliary Control Register on page 4-196
CPACR 2
0x00000000 Architectural Feature Access Control Register on page 4-197
FCSEIDR c13 0 c0 0
0x00000000 FCSE Process ID Register on page 4-267
Table 4-141 Address translation operations
Name CRn Op1 CRm Op2 Reset Width Description
PAR c7 0 c4 0 UNK 32-bit Physical Address Register on page 4-251
- c7 - 64-bit